View PEF2015-TV12_1438364.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ics for communications mini iom ? -2 controller mico pef 2015 version 1.1 data sheet 12.97 ds 1
edition 12.97 this edition was realized using the software system framemaker a . published by siemens ag, hl dt ce ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incur- red. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. pef 2015 revision history: current version: data sheet 12.97 previous version: preliminary data sheet 05.97 page (in previous version) page (in new version) subjects (major changes since last revision) 34, 58 34, 58 mfair: new reset value = 00xx xxxx b 34, 60 34, 60 cififo: new reset value = 0xxx xxxx b 34, 69, 70 34, 69, 70 vnsr register: reset value corrected to 02h (version bits for mico v1.1: 0010) - 75, 78 new timing in motorola mode: t rwh = 10 ns max. (r/w hold time from ds ) 77, 78, 80 75, 76, 78 timing value and definition changed: t dw = 0 ns min. (data set-up time to cs xwr / cs xds in write access)
pef 2015 semiconductor group 3 12.97 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2 pinning diagram (top view) 8 1.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.4 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1 configurable interface cfi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 serial pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.3 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.4 memory structure and switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.5 pre-processed channels, layer-1 support . . . . . . . . . . . . . . . . . . . . . . . .17 2.6 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1 microprocessor interface operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.2 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.4 mico operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4.1 pcm-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4.2 configurable interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.4.3 switching functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.4.4 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.5 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.5.1 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.5.2 mico initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.5.2.1 register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.5.2.2 control memory reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.5.2.3 initialization of pre-processed channels . . . . . . . . . . . . . . . . . . . . .30 3.5.2.4 initialization of the upstream data memory (dm) tristate field . . . .31 3.5.3 activation of the pcm- and cfi-interfaces . . . . . . . . . . . . . . . . . . . . . .32 4 registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.1 register address arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.2.1 pcm-interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.2.1.1 pcm-mode register (pmod) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.2.1.2 bit number per pcm-frame (pbnr) . . . . . . . . . . . . . . . . . . . . . . . .36 4.2.1.3 pcm-offset downstream register (pofd) . . . . . . . . . . . . . . . . . . .36 4.2.1.4 pcm-offset upstream register (pofu) . . . . . . . . . . . . . . . . . . . . .37 4.2.1.5 pcm-clock shift register (pcsr) . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.2.1.6 pcm-input comparison mismatch register (picm) . . . . . . . . . . . . .38
pef 2015 semiconductor group 4 12.97 4.2.2 configurable interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2.2.1 configurable interface mode register 1 (cmd1) . . . . . . . . . . . . . . . 39 4.2.2.2 configurable interface mode register 2 (cmd2) . . . . . . . . . . . . . . . 41 4.2.2.3 configurable interface bit number register (cbnr) . . . . . . . . . . . . 44 4.2.2.4 configurable interface time slot adjustment register (ctar) . . . . 44 4.2.2.5 configurable interface bit shift register (cbsr) . . . . . . . . . . . . . . . 45 4.2.2.6 configurable interface subchannel register ( cscr) . . . . . . . . . . . 47 4.2.3 memory access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.3.1 memory access control register (macr) . . . . . . . . . . . . . . . . . . . . 48 4.2.3.2 memory access address register (maar) . . . . . . . . . . . . . . . . . . . 52 4.2.3.3 memory access data register (madr) . . . . . . . . . . . . . . . . . . . . . . 53 4.2.4 synchronous transfer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.2.4.1 synchronous transfer data register (stda) . . . . . . . . . . . . . . . . . 54 4.2.4.2 synchronous transfer data register b (stdb) . . . . . . . . . . . . . . . . 54 4.2.4.3 synchronous transfer receive address register a (sara) . . . . . . 55 4.2.4.4 synchronous transfer receive address register b (sarb) . . . . . . 56 4.2.4.5 synchronous transfer transmit address register a (saxa) . . . . . 56 4.2.4.6 synchronous transfer transmit address register b (saxb) . . . . . 57 4.2.4.7 synchronous transfer control register (stcr) . . . . . . . . . . . . . . . 57 4.2.5 monitor/feature control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.5.1 mf-channel active indication register (mfair) . . . . . . . . . . . . . . . 58 4.2.5.2 mf-channel subscriber address register (mfsar) . . . . . . . . . . . . 59 4.2.5.3 monitor/feature control channel fifo (mffifo) . . . . . . . . . . . . . . 60 4.2.6 status/control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.6.1 signaling fifo (cififo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.6.2 timer register (timr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.2.6.3 status register (star) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2.6.4 command register (cmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2.6.5 interrupt status register (ista) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2.6.6 mask register mico (mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.6.7 operation mode register (omdr) . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2.6.8 version number status register (vnsr) . . . . . . . . . . . . . . . . . . . . 69 4.3 register changes compared to the epic . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1 pmod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.3.2 pcsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.3.3 picm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.4 cmd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.5 cscr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.3.6 ista . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.7 mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.8 vsnr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 5 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
pef 2015 semiconductor group 5 12.97 5.1 access network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
semiconductor group 6 12.97 pef 2015 overview 1 overview the mini iom-2 controller mico (pef 2015) is an interface controller optimized for small line card applications or intelligent nts. it is derived from the epic core. the mico supports up to 16 analog subscribers (up to 8 using the slicofi) or up to 8 isdn-ba subscribers. the mico is used as an interface device on linecards between the subscriber circuits and the network. therefore it provides one iom-2 interface for connection of up to 8 isdn-ba subscribers or up to 16 analog subscribers (up to 8 using the slicofi).the mico also provides one pcm interface for connection to the main system. additionally the mico is used to control the subscriber circuits via the c/i and monitor channel as specified in the iom-2 specification. a parallel m p interface is provided for device programming. furthermore the mico contains a nonblocking switching unit with a flexible time slot assignment between the iom-2 and the pcm interface. the mico may substitute the epic (peb 2055) or epic-s (peb 2054) in applications that deal with a maximum number of 8 isdn or 16 analog (8 using the slicofi) subscribers connected via one iom-2 port. the mico is fabricated using siemens advanced cmos technology and is available in a p-dso-28 package.
p-dso-28 semiconductor group 7 12.97 mini iom ? -2 controller mico pef 2015 data sheet for the version 1.1 cmos type package pef 2015 p-dso-28 1.1 features functions ? interface controller between iom-2 and pcm for up to 8 isdn-ba or 16 analog subscribers (up to 8 analog subscribers using the slicofi) ? b-channel (64 kbit/s) and d-channel (16 kbit/s) switching ? configurable interface (1 port) - configurable for iom-, sld- and pcm-applications - programmable clock shift - single or double data clock ? pcm interface (1 port) - freely programmable time slot assignment to up to 128 pcm time slots - tristate control signal for external driver - single or double data clock ? c/i-channel handler with a 9-byte fifo ? buffered monitor handler with a 16-byte fifo ? 7-bit hardware timer general ? siemens/intel or motorola type m p interface ? supply voltage: 5 v ? extended temperature range -40c to +85c ? p-dso-28 package
pef 2015 overview semiconductor group 8 12.97 1.2 pinning diagram (top view) figure 1 pinning diagram mic_pinn.drw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 res dd du fsc dcl int cs wr, r/w v ss ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 pdc pfs txd tsc rxd v dd a3 a2 a1 ale, a0 mico rd, ds
pef 2015 overview semiconductor group 9 12.97 1.3 pin description pin no. symbol input (i) output (o) function 23 fsc i/o frame synchronization input or output in iom-configuration. direction indication in sld-mode. 22 dcl i/o data clock input or output in iom-configuration. slave clock in sld mode. single or double data rate in iom-configuration, single data rate in sld-mode. 24 du, sip4 i, i/o (od) data upstream, input iom- or pcm-configuration. serial interface port, sld configuration. 25 dd, sip0 o, i/o (od) data downstream, output iom- or pcm-configuration serial interface port, sld configuration. depending on the bit omdr:cos this line has push-pull or open drain characteristic. for unused or unassigned channels or when bit omdr:csb is reset the pin is in the state high impedance. 7 pfs i pcm-interface frame synchronization 8 pdc i pcm-interface data clock single or double data rate. 6 txd o transmit pcm-interface data time-slot oriented data is shifted out of the micos upstream data memory on this line. for time-slots which are flagged in the tristate data memory or when bit omdr:psb is reset the pin is set in the state high impedance. 5 tsc o tristate control supplies a control signal for an external driver. this line is low when corresponding txd outputs are valid. during reset this line is high. 4 rxd i receive pcm-interface data time-slot oriented data is received on this pin and forwarded into the downstream data memory of the mico.
pef 2015 overview semiconductor group 10 12.97 9 10 11 12 13 14 16 17 ad0, d0 ad1, d1 ad2, d2 ad3, d3 ad4, d4 ad5, d5 ad6, d6 ad7, d7 i/o address/data bus; multiplexed bus mode. transfers addresses from the m p to the mico and data between the m p and the mico. data bus; demultiplexed bus mode. transfers data between the m p and the mico. when driving data the pins have push pull characteristic, otherwise they are in the state high impedance. 2 3 26 27 a0/ale a1 a2 a3 i address bus, demultiplexed mode. transfers addresses from the m p to the mico. address latch enable, multiplexed mode. ale controls the on chip address latch in multiplexed bus mode. while ale is high the latch is transparent. the falling edge latches the current address. note: during reset a0 and a1 are evaluated to determine the bus mode. 18 rd , ds i read, active low, siemens/intel bus mode. when low a read operation is indicated. data strobe, motorola bus mode. a rising edge marks the end of a read or write operation. 19 wr , r/w i write, active low, siemens/intel bus mode. when low a write operation is indicated. read/write, motorola bus mode. when high a valid m p access identifies a read operation, when low it identifies a write access. 20 cs i chip select, active low. a low on this line selects the mico for a read/write operation. pin no. symbol input (i) output (o) function
pef 2015 overview semiconductor group 11 12.97 21 int o (od) interrupt, active low. this line is activated when the mico requests an interrupt. due to the open drain (od) characteristic of int multiple interrupt sources can be connected together. 28 res i reset a high forces the mico into reset state. 15 v ss i ground (0 v) 1v dd i supply voltage (5 v +/- 5%) pin no. symbol input (i) output (o) function
pef 2015 overview semiconductor group 12 12.97 1.4 logic symbol figure 2 logic symbol du dd int cs rd (ds) wr (r/w) ad7..ad0 txd rxd fsc dcl pfs pdc res a3..a0 mico pef 2015 v dd v ss tsc par_log1.drw
pef 2015 overview semiconductor group 13 12.97 1.5 functional block diagram figure 3 functional block diagram p interface du dd mico txd rxd pcm interface upstream (transmit) downstream (receive) access control monitor sync. transfer timer timing fsc dcl pfs pdc res tsc mic_blk3.drw ad7..ad0 a3..a0 dm cm dm cm cfi interface c/i rd (ds) wr (r/w) cs int
pef 2015 functional description semiconductor group 14 12.97 2 functional description 2.1 configurable interface cfi the integrated cfi is a one port serial interface. it comprises two serial data lines (upstream du and downstream dd), a data clock input or output dcl and a frame sync input or output fsc in iom-applications. the clock frequency is either equal to the data rate or twice the data rate. the cfi can be configured to data rates up to 8.192 mbit/s. the cfi is typically used in iom-2 or sld configuration to connect layer-1 devices. figure 4 shows the iom-2 interface structure in line card mode: figure 4 iom ? -2 frame structure with 2.048 mbit/s data rate 2.2 serial pcm interface the pcm interface formats the data transmitted or received at the pcm-highways. it consists of one port comprising a data receive (rxd), a data transmit (txd) and an output tristate indication line (tsc ). the pcm interface is supplied with a frame signal (pfs) and a pcm clock (pdc). data rates up to 8.192 mbit/s are supported. to properly clock the pcm interface a pdc signal with a frequency equal or twice the data rate has to be applied to the mico.
pef 2015 functional description semiconductor group 15 12.97 2.3 microprocessor interface the mico supports siemens/intel and motorola type microprocessors. in the siemens/ intel type m p interface either a multiplexed or a demultiplexed bus structure may be chosen. the interface type is selected by pulling up or down two address pins during the reset state (refer to table 1, selection of bus interface, on page 18 ). pulling-up the appropriate pins selects the motorola type m p interface, fixing them to ground chooses the siemens/intel type m p interface mode. in case of a multiplexed siemens/intel bus structure address pin a0 takes over the ale functionality. the microprocessor interface consists of the following lines: ? data bus, 8-bit wide, ad7..ad0 ? address bus, 4-bit wide, a3..a0 ? chip select, cs ? two read/write control lines: rd and wr (intel mode) or ds and r/w (motorola mode) ? interrupt, int ? reset, res figure 5 selectable bus interface structures 2.4 memory structure and switching the memory block of the mico performs the switching funct ionality. it consists of four sub blocks: C upstream data memory C downstream data memory C upstream control memory C downstream control memory. the pcm-interface reads periodically from the upstream (writes periodically to the downstream) data memory (cyclical access), see figure 6. the cfi reads periodically the control memory and uses the extracted values as a pointers to write to the upstream (read from the downstream) data memory (random bus_intf.drw address/data bus interface, with siemens/intel type mico mico with motorola type interface mico with siemens/intel type address/data bus ds cs d0-7 0-3 ar / w a 0-3 0-7 d cs rd 0-7 ad cs rd ale wr wr demultiplexed multiplexed interface,
pef 2015 functional description semiconductor group 16 12.97 access). in the case of c/i- or signaling channel applications the corresponding data is stored in the control memory. in order to select the application of choice, the control memory provides a code portion. the control memory is accessible via the m p-interface. in order to establish a connection between cfi time slot a and pcm-interface time slot b, the b-pointer has to be loaded into the control memory location a. figure 6 mico memory structure data bits 8 code bits 4 4 bits code 8 bits data data memory (dm) control memory (cm) data bits 8 data memory (dm) (cm) memory control data bits 8 code bits 4 tx d rx d pcm du dd cfi m p upstream downstream
pef 2015 functional description semiconductor group 17 12.97 2.5 pre-processed channels, layer-1 support the mico supports the monitor/feature control and control/signaling channels according to sld- or iom-2 interface protocol. the monitor handler controls the data flow on the monitor/feature control channel either with or without active handshake protocol. to reduce the dynamic load of the cpu a 16-byte transmit/receive fifo is provided. the signaling handler supports different schemes (d-channel + c/i-channel, 6-bit signaling, 8-bit signaling). in downstream direction the relevant content of the control memory is transmitted in the appropriate cfi time slot. in the case of centralized isdn d-channel handling, a 16-kbit/ s d-channel received at the pcm-interface is included. in upstream direction the signaling handler monitors the received data. upon a change it generates an interrupt, the channel address is stored in the 9-byte deep c/i fifo and the actual value is stored in the control memory. in 6-bit and 8-bit signaling schemes a double last look check is provided. 2.6 special functions C synchronous transfer. this utility allows the synchronous m p-access to two independent channels on the pcm- or cfi-interface. interrupts are generated to indicate the appropriate access windows. C 7-bit hardware timer. the mico offers one hardware timer. it can be used to cyclically interrupt the cpu, to determine the double last look period or to generate a proper cfi-multiframe synchronization signal. C frame length checking. the pfs-period is internally checked against the programmed frame length.
semiconductor group 18 12.97 pef 2015 operational description 3 operational description the mico, designed as a flexible line-card controller, has the following main applications: C digital line cards, with the cfi typically configured as iom-2, iom-1 (mux) or sld. C analog line cards, with the cfi typically configured as iom-2 or sld. C intelligent nts, where the micos ability to configure the cfi as a pcm interface is utilized. to operate the mico the user must be fa miliar with the devices microprocessor interface, interrupt structure and reset logic. the device is derived from the epic core. with some restrictions it is therefore programmable like the epic. 3.1 microprocessor interface operation the mico is programmed via an 8-bit parallel interface that can be selected to be (1) motorola type, with control signals ds , r/w , and cs . (2) siemens / intel non-multiple xed bus type, with control signals wr , rd , and cs . (3) siemens / intel multiplexed address/data bus type, with control signals ale, wr , rd , and cs . the selection is performed via supplying address pins a0 and a1 during reset as follows: note: when selecting the mul tiplexed bus m ode, it has to be ensured that during a mico device reset the a0/ale pin receives the appropriate level and no ale transfers by the m c affect the interface type selection (refer also to figure 18 , page 75). when using the siemens / intel multiplexed interface, the mico is addressed with even addresses only (i.e. ad0 always 0), which allows data always to be transferred in the low data byte. this simplifies the use of 16 bit siemens / intel type processors. for a non-multiple xed bus structure the omdr:rbs bit is needed in addition to the address lines a3..0. omdr:rbs (register bank selection) selects one of two register banks. table 1 selection of bus interface a1, a0 during reset bus interface 11 motorola type (1) 00 siemens / intel type, non-multiplexed (2) 01 or 10 siemens / intel type, mul tiplexed (3) pin a0 will take over the ale functionality
pef 2015 operational description semiconductor group 19 12.97 rbs = 1 selects a set of registers used for device initialization (e.g. cfi and pcm interface initialization). rbs = 0 switches to a group of registers necessary during operation (e.g. connection programming). the omdr register containing the rbs bit can be accessed with either value of rbs. interrupts an interrupt of the mico is indicated by activating the int -line. the detailed cause of the request can be determined by reading the ista register. the int -output is level active. it stays active until all interrupt sources have been serviced. if a new status bit is set while an interrupt is being serviced, the int stays active. however, for the duration of a write access to the mask-register the int -line is deactivated. when using an edge-triggered interrupt controller, it is thus recommended to rewrite the mask-register at the end of any interrupt service routine. every interrupt source can be selectively masked by setting the respective bit of the mask-register. such masked interrupts will not be indicated in the ista-register, nor will they activate the int -line. 3.2 clocking to operate properly, the mico always requires a pdc-clock. to synchronize the pcm-side, the mico should normally also be provided with a pfs- strobe. in most applications, the dcl and fsc will be output signals of the mico, derived from the pdc via prescalers. if the required cfi-data rate cannot be derived from the pdc, dcl and fsc can also be programmed as input signals. this is achieved by setting the mico cmd1:css-bit. frequency and phase of dcl and fsc may then be chosen almost independently of the frequency and phase of pdc and pfs. however, the cfi-clock source must still be synchronous to the pcm-interface clock source; i.e. the clock source for the cfi- interface and the clock source for the pcm-interface must be derived from the same master clock. 3.3 reset a reset pulse of at least 4 pdc clock cycles has to be applied at the res pin. the reset pulse sets all registers to their reset values described in section 4 . the mico is now in cm-reset mode (refer to 4.2.6.7 ). as the hardware reset does not affect the mico memories cm and dm, a software reset of the cm has to be performed. subsequently the mico can be programmed to cm-initialization, normal operation or test mode. during reset the address pins a0 and a1 are evaluated to determine the bus interface type.
pef 2015 operational description semiconductor group 20 12.97 3.4 mico operation the mico is principally an intelligent switch of pcm-data between two serial interfaces, the system interface (pcm-interface) and the configurable interface (cfi). up to 128 channels per direction can be switched dynamically between the cfi and the pcm- interfaces. the mico performs non-blocking space and time switching for these channels which may have a bandwidth of 16, 32, 64 or 128 kbit/s on a per device basis. both interfaces can be programmed to operate at different data rates of up to 8.192 mbit/ s. the pcm-interface consists of one duplex port with a tristate control signal. the configurable interface can be selected to provide either one duplex port or two bi- directional (i/o) ports. the configurable interface incorporates a control block (layer-1 buffer) which allows the m p to gain access to the control channels of an iom- (isdn-oriented modular) or sld- (subscriber line data) interface. the mico can handle the layer-1 functions buffering the c/i and monitor channels for iom compatible devices and the feature control and signaling channels for sld compatible devices. the layer-1 and codec devices are connected to the cfi, which is then configured to operate as iom-2, sld or multiplexed iom-1 interface. the configurable interface of the mico can also be configured as plain pcm-interface i.e. without iom- or sld-frame structure. since its possible to operate the two serial interfaces at different data rates, the mico can then be used to adapt two different pcm- systems. the mico can handle up to 8 isdn-subscribers with their 2b+d channel structure or up to 16 analog subscribers with their 1b channel structure in iom-configuration. in sld- configuration up to 4 analog subscribers can be accommodated. the system interface is used for the connection to a pcm-back plane. on a typical digital line card, the mico switches the i sdn b-channels and, if required, also the d-channels to the pcm-back plane. due to its capability to dynamically switch the 16-kbit/s d-channel, the mico is one of the fundamental building blocks for networks with either central, decentral or mixed signaling and packet data handling architecture. 3.4.1 pcm-interface the serial pcm-interface provides one port consisting of a data transmit (txd), a data receive (rxd) and a tristate control (tsc ) line. the transmit direction is also referred to as the upstream direction, whereas the receive direction is referred to as the downstream direction. data is transmitted and received at normal ttl /cmos-levels, the output drivers being of the tristate type. unassigned time slots may either be tristated, or programmed to transmit a defined idle value. the selection of the states "high impedance" and "idle value" can be performed with a two bit resolution. this tristate capability allows several devices to be connected together for concentrator functions. if the output driver
pef 2015 operational description semiconductor group 21 12.97 capability of the mico should prove to be insufficient for a specific application, an external driver controlled by the tsc can be connected. the pcm-standby function makes it possible to switch all pcm-output lines to high impedance with a single command. internally, the device still wo rks normally. only the output drivers are switched off. the number of time slots per 8-khz frame is programmable in a wide range (from 4 to 128). in other words, the pcm-data rate can range between 256 kbit/s up to 8.192 mbit/s . for time slot encoding refer to figure 7 . the number of bits per frame is defined by the pcm-mode. there are three pcm- modes. the timing characteristics at the pcm-interface (data rate, bit shift, etc.) can be varied in a wide range. the pcm-interface has to be clocked with a pcm-data clock (pdc) signal having a frequency equal to or twice the selected pcm-data rate. in single clock rate operation, a frame consisting of 32 time slots, for example, requires a pdc of 2048 khz. in double clock rate operation, however, the same frame structure would require a pdc of 4096 khz. for the synchronization of the time slot structure to an external pcm-system, a pcm- framing signal (pfs) must be applied. the mico evaluates the rising pfs edge to reset the internal time slot counters. in order to adapt the pfs-timing to different timing requirements, the mico can latch the pfs-signal with either the rising or the falling pdc- edge. the pfs-signal defines the position of the first bit of the internal pcm-frame. the actual position of the external upstream and downstream pcm-frames with respect to the framing signal pfs can still be adjusted using the pcm-offset function of the mico. the offset can then be programmed such that pfs marks any bit number of the external frame. furthermore it is possible to select either the rising or falling pdc-clock edge for transmitting and sampling the pcm-data. usually, the repetition rate of the applied framing pulse pfs is identical to the frame period (125 m s). if this is the case, the loss of synchronism indication function can be used to supervise the clock and framing signals for missing or additional clock cycles. the mico checks the pfs-period internally against the d uration expected from the programmed data rate. if, for example, double clock operation with 32 time slots per frame is programmed, the mico expects 512 clock periods within one pfs-period. the synchronous state is reached after the mico has detected two consecutive correct frames. the synchronous state is lost if one bad clock cycle is found. the synchronization status (gained or lost) can be read from an internal register and each status change generates an interrupt.
pef 2015 operational description semiconductor group 22 12.97 figure 7 time slot encoding for the different pcm and cfi modes itd08063mod u/d cfi mode 0 pcm mode 0 1 duplex port 32 time-slots 64 time-slots 1 duplex port u/d u/d 1 duplex port 64 time-slots 128 time-slots 1 duplex port u/d u/d 16 time-slots/port 2 bidirectional ports u/d: upstream (1) / downstream (0) time-slot # (0-31) time-slot # (0-63) time-slot # (0-63) time-slot # (0-127) time-slot # (0-15) cfi mode 1 cfi mode 2 cfi mode 3 pcm mode 2 pcm mode 1 0 0 00 0 1 0 0 0 0
pef 2015 operational description semiconductor group 23 12.97 3.4.2 configurable interface the serial configurable interface (cfi) can be operated either in duplex modes or in a bi- directional mode. in duplex modes the mico provides one port consisting of a data output (dd) and a data input (du) line. the output pin is called "data downstream" pin and the input pin is called "data upstream" pin. these modes are especially suited to realize a standard serial pcm-interface (pcm-highway) or to implement an iom (isdn-oriented modular) interface. the iom-interface generated by the mico offers all the functionality like c/i- and monitor channel handling required for operating all kinds of iom compatible layer-1 and codec devices. in bi-directional mode the mico provides two bi-directional ports (sip). each time slot at any of these ports can individually be programmed as input or output. this mode is mainly intended to realize an sld-interface (serial line data). in case of an sld- interface the frame consists of eight time slots where the first four time slots serve as outputs (downstream direction) and the last four serve as inputs (upstream direction). the sld-interface generated by the mico offers signaling and feature control channel handling. data is transmitted and received at normal ttl/cmos-levels at the cfi. tristate or open-drain output drivers can be selected. in case of open-drain drivers, external pull- up resistors are required. unassigned output time slots may be switched to high impedance or be programmed to transmit a defined idle value. the selection between the states "high impedance" or "idle value" can be performed on a per time slot basis. the cfi-standby function switches all cfi-output lines to high impedance with a single command. internally the device still works normally, only the output drivers are switched off. the number of time slots per 8-khz frame is programmable from 2 to 128. in other words, the cfi-data rate can range between 128 kbit/s up to 8.192 mbit/s . since the mico offers one cfi-port the number of usable memory locations depends on the selected data rate. in duplex modes port 0 has to be programmed, in bi-directional mode i/o port 0 and 4 have to be programmed. for details refer to figure 7 . the timing characteristics at the cfi (data rate, bit shift, etc.) can be varied in a wide range. the clock and framing signals necessary to operate the configurable interface may be derived either from the clock and framing signals of the pcm-interface (pdc and pfs pins), or may be fed in directly via the dcl- and fsc-pins. in the first case, the cfi-data rate is obtained by internally dividing down the pcm-clock signal pdc. several prescaler factors are available to obtain the most commonly used data rates. a cfi reference clock (crcl) is generated out of the pdc-clock. the pcm- framing signal pfs is used to synchronize the cfi-frame structure. additionally, the mico generates clock and framing signals as outputs to operate the connected
pef 2015 operational description semiconductor group 24 12.97 subscriber circuits such as layer-1 and codec filter devices. the generated data clock dcl has a frequency equal to or twice the cfi-data rate. the generated framing signal fsc can be chosen from a great variety of types to suit the different a pplications: iom-2, multiple xed iom-1, sld, etc. note that if pfs is selected as the framing signal source, the fsc-signal is an output with a fixed timing relationship with respect to the cfi-data lines. the relationship between fsc and the cfi-frame depends only on the selected fsc-output wave form (cmd2-register). the cfi-offset function shifts both the frame and the fsc-output signal with respect to the pfs-signal. in the second case, the cfi-data rate is derived from the dcl-clock, which is now used as an input signal. the dcl-clock may also first be divided down by internal prescalers before it serves as the cfi reference clock crcl and before defining the cfi-data rate. the framing signal fsc is used to synchronize the cfi-frame structure. 3.4.3 switching functions the major tasks of the mico is to dynamically switch pcm-data between the serial pcm-interface, the serial configurable interface (cfi) and the parallel m p-interface. all possible switching paths are shown in figure 8 . figure 8 switching paths inside the mico m p m p interface mico 1 2 34 56 cfi pcm
pef 2015 operational description semiconductor group 25 12.97 note that the time slot selections in upstream direction are completely independent of the time slot selections in downstream direction. cfi C pcm time slot assignment switching paths 1 and 2 of figure 8 can be realized for a total number of up to 128 channels per path, i.e. up to 128 time slots in upstream and up to 128 time slots in downstream direction. to establish a connection, the m p writes the addresses of the involved cfi and pcm time slots to the control memory. the actual transfer is then carried out frame by frame without further m p-intervention. the switching paths 5 and 6 can be realized by programming time slot assignments in the control memory. the total number for such loops is limited to the number of available time slots at the respective opposite interface, i.e. looping back a time slot from cfi to cfi requires a spare upstream pcm time slot and looping back a time slot from pcm to pcm requires a spare downstream and upstream cfi time slot. time slot switching is always carried out on 8-bit time slots, the actual position and number of transferred bits can however be limited to 4-bit or 2-bit sub time slots within these 8-bit time slots. on the cfi-side, only one sub time slot per 8-bit time slot can be switched, whereas on the pcm-interface up to 4 independent sub time slots can be switched. examples are given in section 4 of the epic application manual 10.92. sub time slot switching sub time slot positions at the pcm-interface can be selected at random, i.e. each single pcm time slot may contain any mixture of 2- and 4-bit sub time slots. a pcm time slot may also contain more than one sub time slot. on the cfi however, two restrictions must be observed: C each cfi time slot may contain one and only one sub time slot. C the sub-slot position for a given bandwidth within the time slot is fixed on a per port basis and therefore on a per device basis. for more detailed information on sub-channel switching please refer to chapter 5.2 of the epic-1 application manual 10.92. m p-transfer switching paths 3 and 4 of figure 8 can be realized for all available time slots. path 3 can be implemented by defining the corresponding cfi time slots as " m p-channels" or as "pre-processed channels". each single time slot can individually be declared as " m p-channel" . if this is the case, the m p can write a static 8-bit value to a downstream time slot which is then transmitted repeatedly in each frame until a new value is loaded. in upstream direction, the m p can read the received 8-bit value whenever required, no interrupts being generated.
pef 2015 operational description semiconductor group 26 12.97 the "pre-processed channel" option must always be applied to two consecutive time slots. the first of these time slots must have an even time slot number. if two time-slots are declared as "pre-processed channels", the first one can be accessed by the monitor/ feature control handler, which gives access to the frame via a 16-byte fifo. although this function is mainly intended for iom- or sld-applications, it could also be used to transmit or receive a "burst" of data to or from a 64-kbit/s channel. the second pre- processed time slot, the odd one, is also accessed by the m p. in downstream direction a 4-, 6- or 8-bit static value can be transmitted. in upstream direction the received 8-bit value can be read. additionally, a change detection mechanism will generate an interrupt upon a change in any of the selected 4, 6 or 8 bits. pre-processed channels are usually programmed after control memory (cm) reset during device initialization. resetting the cm sets all cfi time slots to unassigned channels (cm code '0000'). of course, pre-processed channels can also be initialized or re-initialized in the operational phase of the device. to program a pair of pre-processed channels the correct code for the selected handling scheme must be written to the cm. figure 9 gives an overview of the available pre- processing codes and their application. for further detail, please refer to chapter 5.5 of the epic users manual 02.97.
pef 2015 operational description semiconductor group 27 12.97 figure 9 pre-processed channel codes
pef 2015 operational description semiconductor group 28 12.97 synchronous transfer for two channels, all switching paths of figure 8 can also be realized using synchronous transfer. the working principle is that the m p specifies an input time slot (source) and an output time slot (destination). both source and destination time slots can be selected independently from each other at either the pcm- or cfi-interfaces. in each frame, the mico first transfers the serial data from the source time slot to an internal data register from where it can be read and if required overwritten or modified by the m p. this data is then fed forward to the destination time slot. chapter 8 of the epic application manual 10.92 provides examples of such transfers. 3.4.4 special functions hardware timer the mico provides one hardware timer which continuously interrupts the m p after a programmable time period. the timer period can be selected in the range of 250 m s up to 32 ms in multiples of 250 m s. beside the interrupt generation, the timer can also be used to determine the last look period for 6 and 8-bit signaling channels on iom-2 and sld-interfaces and for the generation of an fsc-multiframe signal (see chapter 9.1 of the epic application manual 10.92). power and clock supply supervision the connection memory cm is supervised to data falsfication due to clock or power failure. if such an inappropriate clocking or power failure occurs, the m p is requested to reinitialize the device.
pef 2015 operational description semiconductor group 29 12.97 3.5 initialization procedure for proper initialization of the mico the following procedure is recommended: 3.5.1 hardware reset a reset pulse can be applied at the res-pin for at least 4 pdc-clock cycles. the reset pulse sets all registers to their reset values (refer to section 4.1 ). note that in this state dcl and fsc do not deliver any clock signals. 3.5.2 mico initialization 3.5.2.1 register initialization the pcm- and cfi-configuration registers (pmod, pbnr, ? , cmd1, cmd2, ? ) should be programmed to the values required for the application. the correct setting of the pcm- and cfi-registers is important in order to obtain a reference clock (rcl) which is consistent with the exter nally applied clock signals. the state of the operation mode (omdr:oms1..0 bits) does not matter for this programming step. pmod = pcm-mode, timing characteristics, etc. pbnr = num ber of bits per pcm-frame pofd = pcm-offset downstream pofu = pcm-offset upstream pcsr = pcm-timing cmd1 = cfi-mode, timing characteristics, etc. cmd2 = cfi-timing cbnr = num ber of bits per cfi-frame ctar = cfi-of fset (time slots) cbsr = cfi-offset (bits) cscr = cfi-sub channel positions 3.5.2.2 control memory reset since the hardware reset does not affect the mico memories (control and data memories), it is mandatory to perform a "software reset" of the cm. the cm-code '0000' (unassigned channel) should be written to each location of the cm. the data written to the cm-data field is then dont care, e.g. ff h . omdr:oms1..0 must be to '00' b for this procedure (reset value). madr = ff h macr = 70 h wait for star:mac = 0 the resetting of the complete cm takes 256 rcl-clock cycles. during this time, the star:mac-bit is set to logical 1.
pef 2015 operational description semiconductor group 30 12.97 3.5.2.3 initialization of pre-processed channels after the cm-reset, all cfi time slots are unassigned. if the cfi is used as a plain pcm- interface, i.e. containing only switched channels (b-channels), the initialization steps below are not required. the initialization of pre-processed channels applies only to iom- or sld-applications. an iom- or sld-"channel" consists of four consecutive time slots. the first two time slots, the b-channels need not be initialized since they are already set to unassigned channels by the cm-reset command. later, in the application phase of the software, the b-channels can be dynamically switched according to system requirements. the last two time slots of such an iom- or sld-channel, the pre-processed channels must be initialized for the desired functionality. there are four options that can be selec ted: table 2 pre-processed channel options at the cfi also refer to figure 9 . example in cfi-mode 0 the cfi-port shall be initialized as iom-2 port with a 4-bit c/i-field. cfi time slots 0, 1, 4, 5, 8, 9 ? 28, 29 are b-channels and need not to be initialized. cfi time slots 2, 3, 6, 7, 10, 11, ?, 30, 31 are pre-processed channels and need to be initialized: even cfi time slot odd cfi time slot main application monitor/feature control channel monitor/feature control channel monitor/feature control channel monitor/feature control channel 4-bit c/i-channel, d-channel not switched (decentral d-channel handling) 4-bit c/i-channel, d-channel switched (central d-ch. handling) 6-bit sig-channel 8-bit sig/channel iom-1 or iom-2 digital subscriber iom-1 or iom-2 digital subscriber iom-2, analog subscriber sld, analog subscriber
pef 2015 operational description semiconductor group 31 12.97 cfi-port, time slot 2 (even), downstream madr = ff h ; the c/i-value '1111' will be transmitted upon cfi-activation maar = 08 h ; addresses ts 2 down macr = 7a h ; cm-code '1010' wait for star:mac = 0 cfi-port, time slot 3 (odd), downstream madr = ff h ; dont care maar = 09 h ; addresses ts 3 down macr = 7b h ; cm-code '1011' wait for star:mac = 0 cfi-port, time slot 2 (even), upstream madr = ff h ; the c/i-value '1111' is expected upon cfi-activation maar = 88 h ; address ts 2 up macr = 78 h ; cm-code '1000' wait for star:mac = 0 cfi-port, time slot 3 (odd), upstream madr = ff h ; dont care maar = 89 h ; address ts 3 up macr = 70 h ; cm-code '0000' wait for star:mac = 0 repeat the above programming steps for the remaining cfi-time slots. this procedure can be speeded up by selecting the cm-initialization mode (omdr:oms1..0=10). if this selection is made, the access time to a single memory location is reduced to 2.5 rcl-cycles. the complete initialization time for 8 iom-2 channels is then reduced to 32 0.61 m s = 19,5 m s 3.5.2.4 initialization of the upstream data memory (dm) tristate field for each pcm time slot the tristate field defines whether the contents of the dm-data field are to be transmitted (low impedance), or whether the pcm time slot shall be set to high impedance. the content of the tristate field is not modified by a hardware reset. in order to have all pcm time slots set to high impedance upon the activation of the pcm- interface, each location of the tristate field must be loaded with the value '0000'. for this purpose, the "tristate reset" command can be used: omdr = c0 h ; oms1..0 = 11, normal mode madr = 0 0 h ; code field value '0000' b macr = 68 h ; moc-code to initialize all tristate locations (1101 b ) wait for star:mac = 0
pef 2015 operational description semiconductor group 32 12.97 the initialization of the complete tristate field takes 1035 rcl-cycles. note: it is also possible to program the value '1111' to the tristate field in order to have all time slots switched to low impedance upon the activation of the pcm-interface. note: while omdr:psb = 0, all pcm-output drivers are set to high impedance, regardless of the values written to the tristate field. 3.5.3 activation of the pcm- and cfi-interfaces with the mico configured to the system requirements, the pcm- and cfi-interface can be switched to the operational mode. the omdr:oms1..0 bits must be set (if this has not already be done) to the normal operation mode (oms1..0 = 11). when doing this, the pcm-framing interrupt (ista:pfi) will be enabled. if the applied clock and framing signals are in accordance with the values programmed to the pcm-registers, the pfi-interrupt will be gen erated (if not masked). when reading the status register, the star:pss-bit will be set to logical 1. to enable the pcm-output drivers set omdr:psb = 1. the cfi-interface is activated by programming omdr:csb = 1. this enables the output clock and framing signals (dcl and fsc), if these have been programmed as outputs. it also enables the cfi-output drivers. the output driver type can be selected between "open drain" and "tristate" with the omdr:cos-bit. example: activation of the mico for a typical iom-2 application: omdr = ee h ; normal operation mode (oms1..0 = 11) pcm-interface active (psb = 1) pcm-test loop disabled (ptl = 0) cfi-output drivers: open drain (cos = 1) monitor handshake protocol selected (mfps = 1) cfi active (csb = 1) access to mico registers via address pins a3..a0, used in demultiplexed mode only, normal operation (rbs = 0)
pef 2015 registers summary semiconductor group 33 12.97 4 registers summary 4.1 register address arrangement group reg name access address mux ad7..0 address demux omdr:rbs/ a3..0 reset value comment refer to page 1. mico pcm pmod rd/wr 20 h 1/0 h 00 h pcm-mode reg. 35 pbnr rd/wr 22 h 1/1 h ff h pcm-bit number reg. 36 pofd rd/wr 24 h 1/2 h 00 h pcm-offset downstream reg. 36 pofu rd/wr 26 h 1/3 h 00 h pcm-offset upstream reg. 37 pcsr rd/wr 28 h 1/4 h 00 h pcm-clock shift reg. 38 picm rd 2a h 1/5 h xx h dummy 38 2. mico cfi cmd1 rd/wr 2c h 1/6 h 00 h cfi-mode reg. 1 39 cmd2 rd/wr 2e h 1/7 h 00 h cfi-mode reg. 2 41 cbnr rd/wr 30 h 1/8 h ff h cfi-bit number reg. 44 ctar rd/wr 32 h 1/9 h 00 h cfi time slot adjustment reg. 44 cbsr rd/wr 34 h 1/a h 00 h cfi-bit shift reg. 45 cscr rd/wr 36 h 1/b h 00 h cfi-subchannel reg. 47 3. mico memory access macr rd/wr 00 h 0/0 h xx h memory access control reg. 48 maar rd/wr 02 h 0/1 h xx h memory access address reg. 52 madr rd/wr 04 h 0/2 h xx h memory access data reg. 53
pef 2015 registers summary semiconductor group 34 12.97 4. mico synchro nous transfer stda rd/wr 06 h 0/3 h xx h synchron transfer data reg. a 54 stdb rd/wr 08 h 0/4 h xx h synchron transfer data reg. b 54 sara rd/wr 0a h 0/5 h xx h synchron transfer receive address reg. a 55 sarb rd/wr 0c h 0/6 h xx h synchron transfer receive address reg. b 56 saxa rd/wr 0e h 0/7 h xx h synchron transfer transmit address reg. a 56 saxb rd/wr 10 h 0/8 h xx h synchron transfer transmit address reg. b 57 stcr rd/wr 12 h 0/9 h 00xxxx xx synchron transfer control reg. 57 5. mico monitor/ feature control mfair rd 14 h 0/a h 00xxxx xx mf-channel active indication reg. 58 mfsar wr 14 h 0/a h 00 h mf-channel subscriber address reg. 59 mffifo rd/wr 16 h 0/b h xx h mf-channel fifo 60 6. mico status/ control cififo rd 18 h 0/c h 0xxxxx xx signaling channel fifo 60 timr wr 18 h 0/c h 00 h timer reg. 61 star rd 1a h 0/d h 05 h status register 62 cmdr wr 1a h 0/d h 00 h command reg. 63 ista rd 1c h 0/e h 00 h interrupt status 65 mask wr 1c h 0/e h 04 h mask register 66 omdr rd/wr 1e h 3e h x/f h 00 h operation mode reg. 67 vnsr rd 3a h 1/d h 02 h version number status register 69 group reg name access address mux ad7..0 address demux omdr:rbs/ a3..0 reset value comment refer to page
pef 2015 registers summary semiconductor group 35 12.97 4.2 detailed register description unused bits and registers are accessible as described below to facilitate software portation from existing epic designs. they have to be programmed to the specified values. writing other than the specified values may cause undefined behaviour. 4.2.1 pcm-interface registers 4.2.1.1 pcm-mode register (pmod) access in demultiplexed m p-interface mode: read/write address: 0 h , omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 20 h reset value: 00 h pmd1..0 pcm-mode. defines the actual number of pcm-ports, the data rate range and the data rate stepping. pcr pcm-clock rate. 0 single clock rate, data rate is identical with the clock frequency supplied on pin pdc. 1 double clock rate, data rate is half the clock frequency supplied on pin pdc. note: only single clock rate is allowed in pcm-mode 2! psm pcm synchronization mode. a rising edge on pfs synchronizes the pcm-frame. pfs is not evaluated directly but is sampled with pdc. 0 the external pfs is evaluated with the falling edge of pdc. the internal pfs (internal frame start) occurs with the next rising edge of pdc. 1 the external pfs is evaluated with the rising edge of pdc. the internal pfs (internal frame start) occurs with this rising edge of pdc. bit 7 bit 0 pmd1 pmd0 pcr psm 0 0 0 0 pmd1..0 pcm-mode data rate [kbit/s] data rate stepping [kbit/s] min. max. 00 01 10 0 1 2 256 512 1024 2048 4096 8192 256 512 1024
pef 2015 registers summary semiconductor group 36 12.97 4.2.1.2 bit number per pcm-frame (pbnr) access in demultiplexed m p-interface mode: read/write address: 1 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 22 h reset value: ff h bnf7..0 bit number per pcm frame. pcm-mode 0: bnf7..0 = number of bits C 1 pcm-mode 1: bnf7..0 = (number of bits C 2) / 2 pcm-mode 2: bnf7..0 = (number of bits C 4) / 4 the value programmed in pbnr is also used to check the pfs-period. 4.2.1.3 pcm-offset downstream register (pofd) access in demultiplexed m p-interface mode: read/write address: 2 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 24 h reset value: 00 h ofd9..2 offset downstream bit 92. these bits together with pcsr:ofd1 .. 0 determine the offset of the pcm- frame in downstream direction. the following formulas apply for calculating the required register value. bnd is the bit number in downstream direction marked by the rising internal pfs-edge. bpf denotes the actual number of bits constituting a frame. pcm-mode 0: ofd9..2 = mod bpf (bnd C 17 + bpf) pcsr:ofd1..0 = 0 pcm-mode 1: pfd9..1 = mod bpf (bnd C 33 + bpf) pcsr: pfd0 = 0 pcm-mode 2: ofd9..0 = mod bpf (bnd C 65 + bpf) bit 7 bit 0 bnf7 bnf6 bnf5 bnf4 bnf3 bnf2 bnf1 bnf0 bit 7 bit 0 ofd9 ofd8 ofd7 ofd6 ofd5 ofd4 ofd3 ofd2
pef 2015 registers summary semiconductor group 37 12.97 4.2.1.4 pcm-offset upstream register (pofu) access in demultiplexed m p-interface mode: read/write address: 3 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 26 h reset value: 00 h ofu9..2 offset upstream bit 92. these bits together with pcsr:ofu1 .. 0 determine the offset of the pcm- frame in upstream direction. the following formulas apply for calculating the required register value. bnu is the bit number in upstream direction marked by the rising internal pfs-edge. bpf denotes the actual number of bits constituting a frame. pcm-mode 0: ofu9..2 = mod bpf (bnu + 23) pcsr:ofu1..00 = 0 pcm-mode 1: ofu9..1 = mod bpf (bnu + 47) pcsr:ofu0 = 0 pcm-mode 2: ofu9..0 = mod bpf (bnu + 95) bit 7 bit 0 ofu9 ofu8 ofu7 ofu6 ofu5 ofu4 ofu3 ofu2
pef 2015 registers summary semiconductor group 38 12.97 4.2.1.5 pcm-clock shift register ( pcsr) access in demultiplexed m p-interface mode: read/write address: 4 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 28 h reset value: 00 h drcs double rate clock shift. 0...the pcm-input and output data are not delayed 1...the pcm-input and output data are delayed by one pdc-clock cycle ofd1..0 offset downstream bits 10, see pofd-register . dre downstream rising edge. 0the pcm-data is sampled with the falling edge of pdc 1the pcm-data is sampled with the rising edge of pdc adsro add shift register on output. 0...the pcm-output data are not delayed 1...the pcm-output data are delayed by one pdc-clock cycle. note: if both drcs and adsro are set to logical 1, the pcm-output data are delayed by two pdc-clock cycles. ofu1..0 offset upstream bits 10, see pofu-register . ure upstream rising edge. 0the pcm-data is transmitted with the falling edge of pdc 1the pcm-data is transmitted with the rising edge of pdc 4.2.1.6 pcm-input comparison mismatch register (picm) access in demultiplexed m p-interface mode: read address: 5 h omdr:rbs = 1 access in multiplexed m p-interface mode: read address: 2a h reset value: xx h note: this register does not provide valid values for operation. it is a dummy register to facilitate software portation from the epic to the mico. bit 7 bit 0 drcs ofd1 ofd0 dre adsro ofu1 ofu0 ure
pef 2015 registers summary semiconductor group 39 12.97 4.2.2 configurable interface registers 4.2.2.1 configurable interface mode register 1 (cmd1) access in demultiplexed m p-interface mode: read/write address: 6 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 2c h reset value: 00 h css clock source selection. 0pdc and pfs are used as clock and framing source for the cfi. clock and framing signals derived from these sources are output on dcl and fsc. 1dcl and fsc are selected as clock and framing source for the cfi. csm cfi-synchronization mode. the rising fsc-edge synchronizes the cfi-frame. 0fsc is evaluated with every falling edge of dcl. 1fsc is evaluated with every rising edge of dcl. note: if css = 0 is selected, csm and pmod:psm must be programmed identical. csp1..0 clock source prescaler 1,0. the clock source frequency is divided according to the following table to obtain the cfi-reference clock crcl (refer to figures 10 and 11 ). bit 7 bit 0 css csm csp1 csp0 cmd1 cmd0 0 0 csp1,0 prescaler divisor 00 2 01 1.5 10 1 11 not allowed
pef 2015 registers summary semiconductor group 40 12.97 cmd1..0 cfi-mode1,0. defines the actual configuration of the cfi-port. where n = number of time slots in a pcm-frame note: for time slot encoding refer to figure 7 . figure 10 mico clock sources for the cfi and pcm interfaces if cmd1:css = 0 cmd1..0 cfi mode cfi-data rate [kbit/s] min. required cfi-data rate [kbit/s] relative to pcm-data rate necessary reference clock (rcl) dcl-output frequencies cmd1:css = 0 min. max. 00 0 128 2048 32n/3 2xdr dr, 2xdr 01 1 128 4096 64n/3 dr dr 10 2 128 8192 64n/3 0.5xdr dr 11 3 128 1024 16n/3 4xdr dr, 2xdr
pef 2015 registers summary semiconductor group 41 12.97 figure 11 mico clock sources for the cfi and pcm interfaces if cmd1:css = 1 4.2.2.2 configurable interface mode register 2 (cmd2) access in demultiplexed m p-interface mode: read/write address: 7 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 2e h reset value: 00 h fc2..0 framing output control. given that cmd1:css = 0, these bits determine the position of the fsc- pulse relative to the cfi-frame, as well as the type of fsc-pulse generated. the position and width of the fsc-signal with respect to the cfi-frame can be found in the following two figures 12 and 13 . bit 7 bit 0 fc2 fc1 fc0 coc cxf crr cbn9 cbn8
pef 2015 registers summary semiconductor group 42 12.97 figure 12 position of the fsc-signal for fc-modes 0, 1, 2, 3 and 6 figure 13 position of the fsc-signal for fc-modes 4 and 6
pef 2015 registers summary semiconductor group 43 12.97 application examples: for further details on the framing output control please refer to section 2.2.3 of the epic application manual 10.92. coc cfi-output clock rate. 0the frequency of dcl is identical to the cfi-data rate (all cfi-modes), 1the frequency of dcl is twice the cfi-data rate (cfi-modes 0 and 3 only!) note:applies only if cmd1:css = 0. cxf cfi-transmit on falling edge. 0the data is transmitted with the rising crcl edge, 1the data is transmitted with the falling crcl edge. crr cfi-receive on rising edge. 0the data is received with the falling crcl edge, 1the data is received with the rising crcl edge. note:crr must be set to 0 in cfi mode 3. cbn9..8 cfi bit number 9..8 these bits, together with the cbnr:cbn7..0, hold the number of bits per cfi frame. fc2 fc1 fc0 fc-mode main applications 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 iom-1 multiplexed (burst) mode general purpose general purpose general purpose 2 isac-s per sld-port reserved iom-2 or sld-modes software timed multiplexed applications
pef 2015 registers summary semiconductor group 44 12.97 4.2.2.3 configurable interface bit number register (cbnr) access in demultiplexed m p-interface mode: read/write address: 8 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 30 h reset value: ff h cbn7..0 cfi-bit number 7..0. the number of bits that constitute a cfi-frame must be programmed to cbnr:cbn7..0 as indicated below. cbn7..0 = number of bits - 1 for a 8-khz frame structure, the number of bits per frame can be derived from the data rate by division with 8000. 4.2.2.4 configurable interface time slot adjustment register ( ctar) access in demultiplexed m p-interface mode: read/write address: 9 h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 32 h reset value: 00 h tsn6..0 time slot number. the cfi-framing signal (pfs if cmd1:css = 0 or fsc if cmd1:css = 1) marks the cfi time slot called tsn according to the following formula: tsn6 .. 0 = tsn + 2 e.g.: if the framing signal is to mark time slot 0 (bit 7), ctar must be set to 02 h (cbsr to 20 h ). note: if cmd1:css = 0, the cfi-frame will be shifted C together with the fsc-output signal C with respect to pfs. the position of the cfi-frame relative to the fsc- output signal is not affected by these settings, but is instead determined by cmd2:fc2 .. 0. if cmd1:css = 1, the cfi-frame will be shifted with respect to the fsc-input signal. bit 7 bit 0 cbn7 cbn6 cbn5 cbn4 cbn3 cbn2 cbn1 cbn0 bit 7 bit 0 0 tsn6 tsn5 tsn4 tsn3 tsn2 tsn1 tsn0
pef 2015 registers summary semiconductor group 45 12.97 4.2.2.5 configurable interface bit shift register (cbsr) access in demultiplexed m p-interface mode: read/write address: a h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 34 h reset value: 00 h sfsc shift fsc 0...default (behaviour like epic-1 peb 2055) 1...with double clock rate the fsc input is delayed by one cfi clock cycle (iom-2 compatibility) if the bit cbsr:sfsc is set the internal fsc will be delayed by one dcl clock cycle. this enables synchronization in double clock mode with the rising dcl edge according to iom-2. the position of the data bit can now be adjusted using the cfi bit shift functionality as described below. cds2..0 cfi-downstream bit shift 2..0. from the zero offset bit position ( cbsr = 20 h ) the cfi-frame (downstream and upstream) can be shifted by up to 6 bits to the left (within the time slot number tsn programmed in ctar) and by up to 2 bits to the right (within the previous time slot tsn - 1) by programming the cbsr:cds2..0 bits: the bit shift programmed to cbsr:cds2..0 affects both the upstream and downstream frame position in the same way. cus3..0 cfi-upstream bit shift 3..0. these bits shift the upstream cfi-frame relative to the downstream frame by up to 15 bits. for cus3..0 = 0000, the upstream frame is aligned with the downstream frame (no bit shift). bit 7 bit 0 sfsc cds2 cds1 cds0 cus3 cus2 cus1 cus0 cbsr:cds2..0 time slot no. bit no. 000 001 010 011 100 101 110 111 tsn - 1 tsn - 1 tsn tsn tsn tsn tsn tsn 1 0 7 6 5 4 3 2
pef 2015 registers summary semiconductor group 46 12.97 figure 14 internal fsc shift to enable a synchronization with the rising edge of dcl iom_inco.drw dcl d d ext. fsc d u 1st bit 2nd bit 3rd bit 4th bit 5th bit bit 5th bit 4th bit 3rd bit 2nd bit 1st mico external fsc dcl du dd cbsr:sfsc internal fsc d d d u 1st bit 2nd bit 3rd bit 4th bit 5th bit bit 5th bit 4th bit 3rd bit 2nd bit 1st iom-2 specification requirement internal frame start if cbsr:sfsc = 0 d d d u 1st bit 2nd bit 3rd bit 4th bit bit 4th bit 3rd bit 2nd bit 1st cbsr: sfsc = 0 epic behavior int. delayed fsc (cbsr: sfsc = '1') d d d u 1st bit 2nd bit 3rd bit 4th bit bit 4th bit 3rd bit 2nd bit 1st internal frame start if cbsr:sfsc = 1 cbsr:sfsc = 1 shifted 1 bit to the left cbsr:cds2..0 = 011 (cbsr: sfsc = '1')
pef 2015 registers summary semiconductor group 47 12.97 4.2.2.6 configurable interface subchannel register (cscr) access in demultiplexed m p-interface mode: read/write address: b h omdr:rbs = 1 access in multiplexed m p-interface mode: read/write address: 36 h reset value: 00 h sc01..00 cfi-subchannel control for the cfi port. the subchannel control bits sc01..sc00 specify the bit positions to be exchanged with the data memory (dm) when a connection with a channel bandwidth as defined by the cm-code has been establish ed: note: in cfi mode 3 sc01 and sc00 control ports 0 and 4. bit 7 bit 0 0 0 0 0 0 0 sc01 sc00 sc01 sc00 bit positions for cfi subchannels having a bandwidth of 64 kbit/s 32 kbit/s 16 kbit/s 0 0 1 1 0 1 0 1 7..0 7..0 7..0 7..0 7..4 3..0 7..4 3..0 7..6 5..4 3..2 1..0
pef 2015 registers summary semiconductor group 48 12.97 4.2.3 memory access registers 4.2.3.1 memory access control register (macr) access in demultiplexed m p-interface mode: read/write address: 0 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 00 h reset value: xx h with the macr the m p selects the type of memory (cm or dm), the type of field (data or code) and the access mode (read or write) of the register access. when writing to the control memory code field, macr also contains the 4 bit code (cmc3..0) defining the function of the addressed cfi time slot. rws read/write select. 0write operation on control or data memories 1read operation on control or data memories moc3..0 memory operation code. these bits determine the type and destination of the memory operation as shown below. cmc3..0 control memory code. these bits determine the type and destination of the memory operation as shown below. note: prior to a new access to any memory location (i.e. writing to macr) the star:mac bit must be polled for 0. bit 7 bit 0 rws moc3 moc2 moc1 moc0 cmc3 cmc2 cmc1 cmc0
pef 2015 registers summary semiconductor group 49 12.97 1. writing data to the upstream dm-data field (e.g. pcm-idle code). reading data from the upstream or downstream dm-data field. moc3..0 defines the ba ndwidth and the position of the subchannel as shown below: note: when reading a dm-data field location, all 8 bits are read regardless of the bandwidth selected by the moc-bits. 2. writing to the upstream dm-code (tristate) field. control-reading the upstream dm-code (tristate). moc = 1100 read/write tristate info from/to single pcm time slot moc = 1101 write tristate info to all pcm time slots note: the tristate field is exchanged with the 4 least significant bits (lsbs) of the madr. madr:md3 controls the pcm interface function of the bits 7 and 6, md2 of bits 5 and 4, md1 of bits 3 and 2, md0 of bits 1 and 0 (0 = high impedance, 1 = low impedance). 3. writing data to the upstream or downstream cm-data field (e.g. signaling code). reading data from the upstream or downstream cm-data field. macr: rws moc3 moc2 moc1 moc0 0 0 0 moc3..0 transferred bits channel bandwidth 0000 0001 0011 0010 0111 0110 0101 0100 C bits 7..0 bits 7..4 bits 3..0 bits 7..6 bits 5..4 bits 3..2 bits 1..0 C 64 kbit/s 32 kbit/s 32 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s macr: rws moc3 moc2 moc1 moc0 0 0 0 macr: rws1001000
pef 2015 registers summary semiconductor group 50 12.97 4. writing data to the upstream or downstream cm-data and code field (e.g. switching a cfi to/from pcm-connection). the 4-bit code field of the control memory (cm) defines the functionality of a cfi time slot and thus the meaning of the corresponding data field. this 4-bit code, written to the macr:cmc3..0 bit positions, will be transferred to the cm-code field. the 8-bit madr value is at the same time transferred to the cm-data field. there are codes for switching a pplications, pre-processed applications and for direct m p-access applications, as shown below: a) switching applications cmc = 0000 unassigned channel (e.g. cancelling an assigned channel) cmc = 0001 bandwidth 64 kbit/s pcm time slot bits transferred: 7..0 cmc = 0010 bandwidth 32 kbit/s pcm time slot bits transferred: 3..0 cmc = 0011 bandwidth 32 kbit/s pcm time slot bits transferred: 7..4 cmc = 0100 bandwidth 16 kbit/s pcm time slot bits transferred: 1..0 cmc = 0101 bandwidth 16 kbit/s pcm time slot bits transferred: 3..2 cmc = 0110 bandwidth 16 kbit/s pcm time slot bits transferred: 5..4 cmc = 0111 bandwidth 16 kbit/s pcm time slot bits transferred: 7..6 note: the corresponding cfi time slot bits to be transferred are chosen in the cscr-register. b) pre-processed applications downstream: macr: 0 1 1 1 cmc3 cmc2 cmc1 cmc0 application even cm address odd cm address decentral d-channel handling cmc = 1000 cmc = 1011 central d-channel handling cmc = 1010 cmc = pcm-code for a 2-bit subtime slot 6-bit signaling (e.g. analog iom) cmc = 1010 cmc = 1011 8-bit signaling (e.g. sld) cmc = 1010 cmc = 1011
pef 2015 registers summary semiconductor group 51 12.97 upstream: c) m p-access applications setting cmc = 1001, initializes the corresponding cfi time slot to be accessed by the m p. concurrently, the datum in madr is written (as 8-bit cfi-idle code) to the cm-data field. the content of the cm-data field is directly exchanged with the corresponding time slot. note that once the cm-code field has been initialized, the cm-data field can be written and read as described in subsection 3 . 5. control-reading the upstream or downstream cm-code. the cm-code can then be read out of the 4 lsbs of the madr-register. application even cm address odd cm address decentral d-channel handling cmc = 1000 cmc = 0000 central d-channel handling cmc = 1000 cmc = pcm-code for a 2-bit subtime slot 6-bit signaling (e.g. analog iom) cmc = 1010 cmc = 1010 8-bit signaling (e.g. sld) cmc = 1011 cmc = 1011 macr: 0 1111001 macr: 1 1110000
pef 2015 registers summary semiconductor group 52 12.97 4.2.3.2 memory access address register (maar) access in demultiplexed m p-interface mode: read/write address: 1 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 02 h reset value: xx h the memory access address register maar specifies the address of the memory access. this address encodes a cfi time slot for control memory (cm) and a pcm time slot for data memory (dm) accesses. bit 7 of maar (u/d -bit) selects between upstream and downstream memory blocks. bits ma6..0 encode the cfi- or pcm-port and time slot number as in the following tables: table 3 time slot encoding for data memory accesses bit 7 bit 0 u/d ma6 ma5 ma4 ma3 ma2 ma1 ma0 data memory address pcm-mode 0 bit u/d bits ma6..ma3, ma0 bits ma2..ma1 direction selection time slot selection have to be 0 (refer to figure 7 ) pcm-mode 1 bit u/d bits ma6..ma3, ma1, ma0 bit ma2 direction selection time slot selection has to be 0 (refer to figure 7 ) pcm-mode 2 bit u/d bits ma6..ma0 direction selection time slot selection
pef 2015 registers summary semiconductor group 53 12.97 table 4 time slot encoding for control memory accesses 4.2.3.3 memory access data register (madr) access in demultiplexed m p-interface mode: read/write address: 2 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 04 h reset value: xx h the memory access data register madr contains the data to be transferred from or to a memory location. the meaning and the structure of this data depends on the kind of memory being accessed. control memory address cfi-mode 0 bit u/d bits ma6..ma3, ma0 bits ma2..ma1 direction selection time slot selection have to be 0 (refer to figure 7 ) cfi-mode 1 bit u/d bits ma6..ma3, ma2, ma0 bit ma1 direction selection time slot selection has to be 0 (refer to figure 7 ) cfi-mode 2 bit u/d bits ma6..ma0 direction selection time slot selection cfi-mode 3 bit u/d bits ma6..ma4, ma0 bits ma3..ma1 direction selection time slot selection have to be 000 or 100 as only i/o0 and i/o4 are supported bit 7 bit 0 md7 md6 md5 md4 md3 md2 md1 md0
pef 2015 registers summary semiconductor group 54 12.97 4.2.4 synchronous transfer registers 4.2.4.1 synchronous transfer data register (stda) access in demultiplexed m p-interface mode: read/write address: 3 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 06 h reset value: xx h the stda-register buffers the data transferred over the synchronous transfer channel a. mtda7 to mtda0 hold the bits 7 to 0 of the respective time slot. mtda7 (msb) is the bit transmitted/received first, mtda0 (lsb) the bit transmitted/received last over the serial interface. 4.2.4.2 synchronous transfer data register b (stdb) access in demultiplexed m p-interface mode: read/write address: 4 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 08 h reset value: xx h the stdb-register buffers the data transferred over the synchronous transfer channel b. mtdb7 to mtdb0 hold the bits 7 to 0 of the respective time slot. mtdb7 (msb) is the bit transmitted/received first, mtdb0 (lsb) the bit transmitted/received last over the serial interface. bit 7 bit 0 mtda7 mtda6 mtda5 mtda4 mtda3 mtda2 mtda1 mtda0 bit 7 bit 0 mtdb7 mtdb6 mtdb5 mtdb4 mtdb3 mtdb2 mtdb1 mtdb0
pef 2015 registers summary semiconductor group 55 12.97 4.2.4.3 synchronous transfer receive address register a (sara) access in demultiplexed m p-interface mode: read/write address: 5 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 0a h reset value: xx h the sara-register specifies for synchronous transfer channel a from which input interface and time slot the serial data is extracted. this data can then be read from the stda-register. isra interface select receive for channel a. 0 selects the pcm-interface as the input interface for synchronous channel a. 1 selects the cfi-interface as the input interface for synchronous channel a. mtra6..0 m p-transfer receive address for channel a; selects the port and time slot number at the interface selected by isra according to tables 3 and 4 : mtra6..0 = ma6..0. bit 7 bit 0 isra mtra6 mtra5 mtra4 mtra3 mtra2 mtra1 mtra0
pef 2015 registers summary semiconductor group 56 12.97 4.2.4.4 synchronous transfer receive address register b (sarb) access in demultiplexed m p-interface mode: read/write address: 6 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 0c h reset value: xx h the sarb-register specifies for synchronous transfer channel b from which input interface and time slot the serial data is extracted. this data can then be read from the stdb register. isrb interface select receive for channel b. 0 selects the pcm-interface as the input interface for synchronous channel b. 1 selects the cfi-interface as the input interface for synchronous channel b. mtrb6..0 m p-transfer receive address for channel b; selects the port and time slot number at the interface selected by isrb according to tables 3 and 4 : mtrb6..0 = ma6..0. 4.2.4.5 synchronous transfer transmit address register a (saxa) access in demultiplexed m p-interface mode: read/write address: 7 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 0e h reset value: xx h the saxa-register specifies for synchronous transfer channel a to which output interface and time slot the serial data contained in the stda-register is sent. isxa interface select transmit for channel a. 0 selects the pcm-interface as the output interface for synchronous channel a. 1 selects the cfi-interface as the output interface for synchronous channel a. mtxa6..0 m p-transfer transmit address for channel a; selects the port and time slot number at the interface selected by isxa according to tables 3 and 4 : mtxa6..0 = ma6..0. bit 7 bit 0 isrb mtrb6 mtrb5 mtrb4 mtrb3 mtrb2 mtrb1 mtrb0 bit 7 bit 0 isxa mtxa6 mtxa5 mtxa4 mtxa3 mtxa2 mtxa1 mtxa0
pef 2015 registers summary semiconductor group 57 12.97 4.2.4.6 synchronous transfer transmit address register b (saxb) access in demultiplexed m p-interface mode: read/write address: 8 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 10 h reset value: xx h the saxb-register specifies for synchronous transfer channel b to which output interface and time slot the serial data contained in the stdb-register is sent. isxb interface select transmit for channel b. 0 selects the pcm-interface as the output interface for synchronous channel b. 1 selects the cfi-interface as the output interface for synchronous channel b. mtxb6..0 m p-transfer transmit address for channel b; selects the port and time slot number at the interface selected by isxb according to tables 3 and 4 : mtxb6..0 = ma6..0. 4.2.4.7 synchronous transfer control register (stcr) access in demultiplexed m p-interface mode: read/write address: 09 h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 12 h reset value: 00xxxxxx b the stcr-register bits are used to enable or disable the synchronous transfer utility and to determine the sub time slot bandwidth and position if a pcm-interface time slot is involved. tae, tbe transfer channel a (b) enable. 1 enables the m p transfer of the corresponding channel. 0 disables the m p transfer of the corresponding channel. bit 7 bit 0 isxb mtxb6 mtxb5 mtxb4 mtxb3 mtxb2 mtxb1 mtxb0 bit 7 bit 0 tbe tae ctb2 ctb1 ctb0 cta2 cta1 cta0
pef 2015 registers summary semiconductor group 58 12.97 cta2..0 channel type a (b); these bits determine the bandwidth of the channel and ctb2..0 the position of the relevant bits in the time slot according to the table below. note: if a cfi time slot is selected as receive or transmit time slot of the synchronous transfer, the 64-kbit/s bandwidth must be selected (ct#2..ct#0 = 001). 4.2.5 monitor/feature control registers 4.2.5.1 mf-channel active indication register (mfair) access in demultiplexed m p-interface mode: read address: a h omdr:rbs = 0 access in multiplexed m p-interface mode: read address: 14 h reset value: 00xx xxxx b this register is only used in iom-2 applications (active handshake protocol) in order to identify active monitor channels when the "search for active monitor channels" command (cmdr:mfso) has been executed. so mf channel search on. 0the search is completed. 1the mico is still busy looking for an active channel. sad5..0 subscriber address 5..0; after an ista:mac-interrupt these bits point to the time slot where an active channel has been found. the coding is identical to mfsar:sad5..sad0. ct#2 ct#1 ct#0 bandwidth transferred bits 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 not allowed 64 kbit/s 32 kbit/s 32 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s C bits 7..0 bits 3..0 bits 7..4 bits 1..0 bits 3..2 bits 5..4 bits 7..6 bit 7 bit 0 0 so sad5 sad4 sad3 sad2 sad1 sad0
pef 2015 registers summary semiconductor group 59 12.97 4.2.5.2 mf-channel subscriber address register (m fsar) access in demultiplexed m p-interface mode: write address: a h omdr:rbs = 0 access in multiplexed m p-interface mode: write address: 14 h reset value: xx h the exchange of monitor data normally takes place with only one subscriber circuit at a time. this register serves to point the mf-handler to that particular cfi time slot. mftc1..0 mf channel transfer control 1..0; these bits, in addition to cmdr:mft1,0 and omdr:mfps control the mf-channel transfer as indicated in table 5 . sad5..0 subscriber address 5..0; these bits define the addressed subscriber. the cfi time slot encoding is similar to the one used for control memory accesses using the maar-register ( tables 3 and 4 ): cfi time slot encoding of mfsar derived from maar: maar:ma7 selects between upstream and downstream cm-blocks. this information is not required since the transfer direction is defined by cmdr (transmit or receive). maar:ma0 selects between even and odd time slots. this information is also not required since mf-channels are always located on even time slots. bit 7 bit 0 mftc1 mftc0 sad5 sad4 sad3 sad2 sad1 sad0 maar: ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 mfsar: mftc1 mftc0 sad5 sad4 sad3 sad2 sad1 sad0
pef 2015 registers summary semiconductor group 60 12.97 4.2.5.3 monitor/feature control channel fifo (mffifo) access in demultiplexed m p-interface mode: read/write address: b h omdr:rbs = 0 access in multiplexed m p-interface mode: read/write address: 16 h reset value: xx h the 16-byte bi-directional mffifo provides intermediate storage for data bytes to be transmitted or received over the monitor or feature control channel. mfd7..0 mf data bits 7..0; mfd7 (msb) is the first bit to be sent over the serial cfi, mfd0 (lsb) the last. note: the byte n+1 of an n-byte transmit message in monitor channel is not defined. 4.2.6 status/control registers 4.2.6.1 signaling fifo (cififo) access in demultiplexed m p-interface mode: read address: c h omdr:rbs = 0 access in multiplexed m p-interface mode: read address: 18 h reset value: 0xxxxxxx b the 9 byte deep cififo stores the addresses of cfi time slots in which a c/i- and/or a sig-value change has taken place. this address information can then be used to read the actual c/i- or sig-value from the control memory. sbv signaling byte valid. 0 the sad6..0 bits are invalid. 1 the sad6..0 bits indicate a valid subscriber address. the polarity of sbv is chosen such that the whole 8 bits of the cififo can be copied to the maar register in order to read the upstream c/i- or sig-value from the control memory. sad6..0 subscriber address bits 6..0; the cm-address which corresponds to the cfi time slot where a c/i- or sig-value change has taken place is encoded in these bits. for c/i-channels sad6..0 point to an even cm-address (c/ bit 7 bit 0 mfd7 mfd6 mfd5 mfd4 mfd3 mfd2 mfd1 mfd0 bit 7 bit 0 sbv sad6 sad5 sad4 sad3 sad2 sad1 sad0
pef 2015 registers summary semiconductor group 61 12.97 i-value), for sig-channels sad6..0 point to an odd cm-address (stable sig- value). 4.2.6.2 timer register (timr) access in demultiplexed m p-interface mode: write address: c h omdr:rbs = 0 access in multiplexed m p-interface mode: write address: 18 h reset value: 00 h the mico timer can be used for 3 different purposes: timer interrupt generation (ista:tig), fsc multiframe generation (cmd2:fc2..0 = 111) and last look period generation. ssr signaling sampling rate. 0 the last look period is defined by tval6..0. 1 the last look period is fixed to 125 m s. tval6..0 timer value bits 6..0; the timer period, equal to (1+tval6..0) 250 m s, is programmed here. it can thus be adjusted within the range of 250 m s up to 32 ms. the timer is started as soon as cmdr:st is set to 1 and stopped by writing the timr-register or by selecting omdr:oms0 = 0. bit 7 bit 0 ssr tval6 tval5 tval4 tval3 tval2 tval2 tval0
pef 2015 registers summary semiconductor group 62 12.97 4.2.6.3 status register (star) access in demultiplexed m p-interface mode: read address: d h omdr:rbs = 0 access in multiplexed m p-interface mode: read address: 1a h reset value: 05 h the status register star displays the current state of certain events within the mico. the star register bits do not generate interrupts and are not modified by reading star. mac memory access 0 no memory access is in operation. 1 a memory access is in operation. hence, the memory access registers may not be used. note: mac is also set and reset during synchronous transfers. tac timer active 0 the timer is stopped. 1 the timer is running. pss pcm-synchronization status. 1 the pcm-interface is synchronized. 0 the pcm-interface is not synchronized. there is a mismatch between the pbnr-value and the applied clock and framing signals (pdc/pfs) or omdr:oms0 = 0. mfto mf-channel transfer in operation. 0 no mf-channel transfer is in operation. 1 an mf-channel transfer is in operation. mfab mf-channel transfer aborted. 0 the remote receiver did not abort a handshake message transfer. 1 the remote receiver aborted a handshake message transfer. mfae mffifo-access enable. 0 the mffifo may not be accessed. 1 the mffifo may be either read or written to. mfrw mffifo read/write. 0 the mffifo is ready to be written to. 1 the mffifo may be read. mffe mffifo empty 0 the mffifo is not empty. 1 the mffifo is empty. bit 7 bit 0 mac tac pss mfto mfab mfae mfrw mffe
pef 2015 registers summary semiconductor group 63 12.97 4.2.6.4 command register (cmdr) access in demultiplexed m p-interface mode: write address: d h omdr:rbs = 0 access in multiplexed m p-interface mode: write address: 1a h reset value: 00 h writing a logical 1 to a cmdr-register bit starts the respective operation. st start timer. 0 no action. if the timer shall be stopped, the timr-register must simply be written with a random value. 1 starts the timer to run cyclically from 0 to the value programmed in timr:tval6..0. tig timer interrupt generation. 0 setting the tig-bit to logical 0 together with the cmdr:st-bit set to logical 1 disables the interrupt generation. 1 setting the tig-bit to logical 1 together with cmdr:st-bit set to logical 1 causes the mico to generate a periodic interrupt (ista:tin) each time the timer expires. cfr cififo reset. 0 no action. 1 resets the signaling fifo within 2 rcl-periods, i.e. all entries and the ista:sfi-bit are cleared. mft1..0 mf-channel transfer control bits 1,0; these bits start the monitor transfer enabling the contents of the mffifo to be exchanged with the subscriber circuits as specified in mfsar. the function of some commands depends furthermore on the selected protocol (omdr:mfps). table 5 summarizes all available mf-commands. mfso mf-channel search on. 0 no action. 1 the mico starts to search for active mf-channels. active channels are characterized by an active mx-bit (logical 0) sent by the remote transmitter. if such a channel is found, the corresponding address is stored in mfair and an ista:mac-interrupt is generated. the search is stopped when an active mf-channel has been found or when omdr:oms0 is set to 0. bit 7 bit 0 0 st tig cfr mft1 mft0 mfso mffr
pef 2015 registers summary semiconductor group 64 12.97 mffr mffifo reset. 0 no action 1 resets the mffifo and all operations associated with the mf-handler (except for the search function) within 2 rcl-periods. the mffifo is set into the state "mffifo empty", write access enabled and any monitor data transfer currently in process will be aborted. table 5 summary of mf-channel commands hs: handshake facility enabled (omdr:mfps = 1) no hs: handshake facility disable (omdr:mfps = 0) transfer mode cmdr: mft1,mft0 mfsar prot ocol selection application inactive 00 xxxxxxxx hs, no hs idle state transmit 01 00 sad5..0 hs, no hs iom-2, iom-1, sld transmit broadcast 01 01xxxxxx hs, no hs iom-2, iom-1, sld test operation 01 10------ hs, no hs iom-2, iom-1, sld transmit continuous 11 00 sad5..0 hs iom-2 transmit + receive same time slot any # of bytes 1 byte expected 2 bytes expected 8 bytes expected 16 bytes expected 10 10 10 10 10 00 sad5..0 00 sad5..0 01 sad5..0 10 sad5..0 11 sad5..0 hs no hs no hs no hs no hs iom-2 iom-1 (iom-1) (iom-1) (iom-1) transmit + receive same line 1 byte expected 2 bytes expected 8 bytes expected 16 bytes expected 11 11 11 11 00 sad5..0 01 sad5..0 10 sad5..0 11 sad5..0 no hs no hs no hs no hs sld sld sld sld
pef 2015 registers summary semiconductor group 65 12.97 4.2.6.5 interrupt status register (ista) access in demultiplexed m p-interface mode: read address: e h omdr:rbs = 0 access in multiplexed m p-interface mode: read address: 1c h reset value: 00 h the ista-register should be read after an interrupt in order to determine the interrupt source. tin timer interrupt; a timer interrupt previously requested with cmdr:st,tig = 1 has occurred. the tin-bit is reset by reading ista. it should be noted that the interrupt generation is periodic, i.e. unless stopped by writing to timr, the ista:tin will be gen erated each time the timer expires. sfi signaling fifo-interrupt; this interrupt is generated if there is at least one valid entry in the cififo indicating a change in a c/i- or sig-channel. reading ista does not clear the sfi-bit. instead sfi is cleared if the cififo is empty which can be accomplished by reading all valid entries of the cififo or by resetting the cififo by setting cmdr:cfr to 1. mffi mffifo-interrupt; the last mf-channel command (issued by cmdr:mft1,mft0) has been executed and the mico is ready to accept the next command. additional information can be read from star:mftomffe. mffi is reset by reading ista. mac monitor channel active interrupt; the mico has found an active monitor channel. a new search can be started by reissuing the cmdr:mfso- command. mac is reset by reading ista. pfi pcm-framing interrupt; the star:pss-bit has changed its polarity. to determine whether the pcm-interface is synchronized or not, star must be read. the pfi-bit is reset by reading ista. sin synchronous transfer interrupt; the sin-interrupt is enabled if at least one synchronous transfer channel (a and/or b) is enabled via the stcr:tae, tbe-bits. the sin-interrupt is generated when the access window for the m p opens. after the occurrence of the sin-interrupt the m p can read and/or write the synchronous transfer data registers (stda, stdb). the sin-bit is reset by reading ista. bit 7 bit 0 tin sfi mffi mac pfi 0 sin sov
pef 2015 registers summary semiconductor group 66 12.97 sov synchronous transfer overflow; the sov-interrupt is generated if the m p fails to acc ess the data registers (stda, stdb) within the access window. the sov-bit is reset by reading ista. 4.2.6.6 mask register mico (mask) access in demultiplexed m p-interface mode: write address: e h omdr:rbs = 0 access in multiplexed m p-interface mode: write address: 1c h reset value: 00 h a logical 1 disables the corresponding interrupt as described in the ista-register. a masked interrupt is stored internally and reported in ista immediately if the mask is released. however, an sfi-interrupt is also reported in ista if masked. in this case no interrupt is generated. when writing register mask while ista indicates a non masked interrupt, int is temporarily set into the inactive state. bit 7 bit 0 tin sfi mffi mac pfi 1 sin sov
pef 2015 registers summary semiconductor group 67 12.97 4.2.6.7 operation mode register (omdr) access in demultiplexed m p-interface mode: read/write address: f h omdr:rbs = x access in multiplexed m p-interface mode: read/write address: 1e h /3e h reset value: 00 h oms1..0 operational mode selection; these bits determine the operation mode of the mico is working in according to the following table: bit 7 bit 0 oms1 oms0 psb ptl cos mfps csb rbs oms1..0 function 00 the cm-reset mode is used to reset all locations of the control memory code and data fields with a single comm and within only 256 rcl-cycles. a typical application is resetting the cm with the command macr = 70 h which writes the contents of madr (xx h ) to all data field locations and the code '0000' (unassigned channel) to all code field locations. a cm-reset should be made after each hardware reset. in the cm-reset mode the mico does not operate normally i.e. the cfi- and pcm-interfaces are not operational. 10 the cm-initialization mode allows fast programming of the control memory since each memory access takes a maximum of only 2.5 rcl-cycles compared to the 9.5 rcl-cycles in the normal mode. accesses are performed on individual addresses specified by maar. the initialization of control/signaling channels in iom- or sld- applications can for example be carried out in this mode. in the cm- initialization mode the mico does also not work normally. 11 in the normal operation mode the cfi- and pcm-interfaces are operational. memory accesses performed on single addresses (specified by maar) take 9.5 rcl-cycles. an ini tialization of the complete data memory tristate field takes 1035 rcl-cycles. 01 in test mode the mico sustains normal operation. however memory accesses are no longer performed on a specific address defined by maar, but on all locations of the selected memory, the contents of maar (including the u/d-bit!) being ignored. a test mode access takes 2057 rcl-cycles.
pef 2015 registers summary semiconductor group 68 12.97 psb pcm-standby. 0the pcm-interface output pin txd is set to high impedance and if the tsc -pin is actually used as tristate control signal it is set to logical 1 (inactive). 1the pcm-output pin transmits the contents of the upstream data memory or may be set to high impedance via the data memory tristate field. ptl pcm-test loop. 0the pcm-test loop is disabled. 1the pcm-test loop is enabled, i.e. the physical transmit pin txd is internally connected to the corresponding physical receive pin rxd, such that data transmitted over txd are internally looped back to rxd and data externally received over rxd are ignored. the txd pin still outputs the contents of the upstream data memory according to the setting of the tristate field (only modes 0 and 1; mode 1 with ais-bit set). cos cfi-output driver selection. 0the cfi-output drivers are tristate drivers. 1the cfi-output drivers are open drain drivers. mfps monitor/feature control channel protocol selection 0...handshake facility disabled (sld and iom-1 applications). 1...handshake facility enabled (iom-2 applications). csb cfi-standby. 0the cfi-interface output pins dd, du, dcl and fsc are set to high impedance. 1the cfi-output pins are active. rbs register bank selection. used in demultiplexed data/address modes only. 0to access the registers used during device operation. 1to access the registers used during device initialization
pef 2015 registers summary semiconductor group 69 12.97 4.2.6.8 version number status register (vnsr) access in demultiplexed m p-interface mode: read address: d h omdr:rbs = 1 access in multiplexed m p-interface mode: read address: 3a h reset value: 02 h the vn3..0 bits are read only bits. ir initialization request; this bit is set to logical 1 after an inappropriate clocking or after a power failure. it is reset to logical 0 after a control memory reset command: omdr:oms1..0 = 00, macr = 7x h . vn3..0 version status number; these bits display the mico chip version as follows bit 7 bit 0 ir 0 0 0 vn3 vn2 vn1 vn0 vn3..0 chip versions 0010 v1.1
pef 2015 registers summary semiconductor group 70 12.97 4.3 register changes compared to the epic 4.3.1 pmod ais1..0 have to be programmed to 00 aic1..0 have to be programmed to 00 (no alternate input comparison supported). 4.3.2 pcsr drcs added. adsro added. 4.3.3 picm values are not valid for operation. 4.3.4 cmd1 cis1..0 have to be programmed to 00 (in cfi modes 0, 1 and 2 always logical port 0 is selected). 4.3.5 cscr sc31..30 have to be programmed to 00 (only port 0 supported). sc21..20 sc11..10 4.3.6 ista pim not valid for operation (pcm input mismatch not supported as only one pcm input line is provided). 4.3.7 mask pim has to be programmed to 1 (pim interrupt masked, refer to 4.3.6 ). 4.3.8 vsnr vn3..0 fixed to 0010 (mico v1.1).
semiconductor group 71 12.97 pef 2015 application examples 5 application examples 5.1 access network access networks are used in order to connect subscribers to the telecom network quickly and at low cost. one possibility is to use the existing cable tv network to provide telephony services. an existing hybrid fiber-coaxial network (hfcn) that has been upgraded for upstream communication is the basis for such an access network. figure 15 illustrates the functional model of an optical access network (fiber in the loop fitl). figure 15 functional model of an optical access network the master headend will serve one or multiple main distribution frames. via the hfcn the uie is provided. depending on the number of supported user ports and how far the fiber is available, the configuration is called fiber to the home (ftth), fiber to the building (fttb) or fiber to the curb (fttc). the mico can be used in a configuration where a maximum of 16 pots or 8 isdn subscribers are needed, e.g. ftth or fttb applications. figure 16 shows an example of an user interface equipment (uie) providing two pots and one isdn subscriber. uie main hfcn: hybrid fiber-coaxial network master headend olt digital local core network exchange hfcn frame uie: user interface equipment olt: optical line termination hfcn hfcn distribution
pef 2015 application examples semiconductor group 72 12.97 figure 16 example using the mico in an uie the mico will replace the epic in applications where only a few subscribers have to be supported. it connects the subscriber circuits to the hf unit providing switching capability. additionally the subscriber circuits are controlled via the implemented c/i- and monitor-handlers. mico tuner modulation rf interface m c slicofi slicofi hv slic hv slic iec-q iom-2 pcm 2 pots isdn
semiconductor group 73 12.97 pef 2015 electrical characteristics 6 electrical characteristics note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. dc characteristics absolute maximum ratings parameter symbol limit values unit ambient temperature under bias: pef t a - 40 to 85 c storage temperature t stg - 65 to 125 c voltage on any pin with respect to ground v s - 0.4 to v dd + 0.4 v maximum voltage on any pin v max 6v pef: t a = - 40 to 85 c; v dd = 5 v 5 %; v ss = 0 v parameter symbol limit values unit test condition min. max. l-input voltage v il - 0.4 0.8 v h-input voltage v ih 2.2 v dd + 0.4 v l-output voltage v ol 0.45 v i ol = 7 ma (pins du, dd) i ol = 2 ma (all other) h-output voltage h-output voltage v oh v oh 2.4 3.5 v v i oh = - 400 m a i oh = - 200 m a power supply current operational i cc i cc 9.5 6.5 ma ma v dd = 5 v, inputs at 0 v or v dd , no output loads pdc > 4.096 mhz pdc 4.096 mhz input leakage current output leakage current i li i lo 1 1 m a m a 0 v < v in < v dd to 0 v 0 v < v out < v dd to 0 v
pef 2015 electrical characteristics semiconductor group 74 12.97 note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. capacitances ac-characteristics ambient temperature under bias range, v dd = 5 v 5 %. inputs are driven to 2.4 v for a logical '1' and to 0.4 v for a logical '0'. timing measurements are made at 2.0 v for a logical '1' and at 0.8 v for a logical '0'. the ac-testing input/output wave forms are shown below. figure 17 i/o-wave form for ac-test t a = 25 c; v dd = 5 v 5 %, v ss = 0 v, f c = 1 mhz, unmeasured pins returned to v ss . parameter symbol limit values unit min. max. input capacitance, f c = 1 mhz c in 510pf output capacitance c out 8 15 pf i/o capacitance c i/o 10 20 pf under device test its09737 100 pf c l = 2.4 v 0.4 v test points 2.0 v 0.8 v 0.8 v 2.0 v
pef 2015 electrical characteristics semiconductor group 75 12.97 bus interface timing figure 18 microprocessor interface selection: address hold time after reset parameter symbol limit values unit min. max. r or w set-up to ds t dsd 0ns r or w hold time from ds t rwh 10 ns rd -pulse width t rr 80 ns rd -control interval t ri 40 ns data output delay from rd t rd 80 ns data float delay from rd t df 25 ns wr -pulse width t ww 45 ns wr -control interval t wi 40 ns data set-up time to wr xcs , ds xcs t dw 0ns data hold time from wr xcs , ds xcs t wd 15 ns ale-pulse width t aa 30 ns address set-up time to ale t al 10 ns address hold time from ale t la 15 ns ale set-up time to wr , rd t als 8ns address set-up time to wr , rd t as 10 ns address hold time from wr , rd t ah 0ns address hold time after reset t ahr 10 ns a1, a0 res t ahr up_sel.drw
pef 2015 electrical characteristics semiconductor group 76 12.97 figure 19 a siemens/intel bus mode itt05854mod t rr t ri t rd data cs x rd d0- m p read cycle d7 t df itt05855mod t ww t wi dw t t wd data cs xwr m p write cycle d0- d7 itt05856mod address t al t la wr x cs cs xrd address timing multiplexed bus mode t aa t als ale ad 0- ad 7
pef 2015 electrical characteristics semiconductor group 77 12.97 figure 19 b siemens/intel bus mode itt05857mod address t as t ah rd x cs cs xwr a0 - a 3
pef 2015 electrical characteristics semiconductor group 78 12.97 figure 20 motorola bus mode t5858mod t dsd t rr t ri r / w cs x ds m p read cycle data t rd t df d0 -d7 t rwh t5859mod t dsd t ww t wi r / w cs x ds d0 m p write cycle d7 - dw t t wd data t rwh t5860mod t ah t as address address tim ing ds x cs - 3 a 0 a
pef 2015 electrical characteristics semiconductor group 79 12.97 pcm and configurable interface timing parameter symbol limit values unit test conditions min. max. clock period t cp 240 ns clock frequency 4096 khz clock period low t cpl 80 ns clock period high t cph 100 ns clock period t cp 120 ns clock frequency > 4096 khz clock period low t cpl 50 ns clock period high t cph 50 ns frame set-up time to clock t fs 25 ns frame hold time from clock t fh 50 ns data clock delay t dcd 125 ns serial data input set-up time t s 7ns pcm-input data frequency > 4096 kbit/s serial data hold time t h 35 ns serial data input set-up time t s 15 ns pcm-input data frequency 4096 kbit/s serial data hold time t h 55 ns serial data input set-up time t s 20 ns cfi-input data frequency > 4096 kbit/s serial data hold time t h 50 ns serial data input set-up time t s 0ns cfi-input data frequency 4096 kbit/s serial data hold time t h 75 ns pcm-serial data output delay t d 55 ns tristate control delay t t 60 ns cfi-serial data output delay t cdf 65 ns falling clock edge cfi-serial data output delay t cdr C 90 ns rising clock edge
pef 2015 electrical characteristics semiconductor group 80 12.97 figure 21 configurable interface timing, cmd:csp1,0 = 10 (prescalor divisor = 1)
pef 2015 electrical characteristics semiconductor group 81 12.97 figure 22 configurable interface timing, cmd:csp1,0 = 01 (prescalor divisor = 1,5)
pef 2015 electrical characteristics semiconductor group 82 12.97 figure 23 configurable interface timing, cmd:csp1,0 = 00 (prescalor divisor = 2)
pef 2015 electrical characteristics semiconductor group 83 12.97 figure 24 pcm-interface timing itd05871 1 bit of frame st 2 nd 3 rd t fh t fh t fs t fs t fs t fh t fh t d t t h t t t h t s h t s t t s t h t cp t cpl cph t frame of bit frame of bit t fs st frame of bit 1 d t 1 bit of frame st bit st 1 of frame 1 st bit of frame frame of 1 st bit frame of bit st 1 d t pdc pmod : pcr = 0 pfs (pmod:psm=0) st frame of bit 1 bit of frame 1 st d t s t t frame of bit st 1 t t t t st 1 bit of frame (pmod:psm=1) pfs (pcsr:ure=1) txd tsc (pcsr:ure=1) (pcsr:dre=0) rxd txd (pcsr:ure=0) (pcsr:ure=0) tsc rxd (pcsr:dre=1) (pcsr:ure=1) txd (pcsr:ure=1) tsc (pcsr:dre=0) rxd (pcsr:ure=0) txd tsc (pcsr:ure=0) (pcsr:dre=1) rxd 1 = pcr : pmod
pef 2015 package outlines semiconductor group 84 12.97 7 package outlines p-dso-28 (plastic dual small outline) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

▲Up To Search▲

Price & Availability of PEF2015-TV12

	To Download PEF2015-TV12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .